MAX96718打pattern方法

效果

code

$cat pattern_generator_max96718.c /* SPDX-License-Identifier: GPL-2.0 */ #ifndef __MAXIM2C_API_H__ #define __MAXIM2C_API_H__ #include <stdbool.h> //#include "maxim2c_i2c.h" #ifndef __MAXIM2C_I2C_H__ #define __MAXIM2C_I2C_H__ //#include <linux/i2c.h> #include <stdint.h> #define u8 uint8_t #define u16 uint16_t #define u32 uint32_t /* register address: 8bit or 16bit */ #define MAXIM2C_I2C_REG_ADDR_08BITS 1 #define MAXIM2C_I2C_REG_ADDR_16BITS 2 /* register value: 8bit or 16bit or 24bit */ #define MAXIM2C_I2C_REG_VALUE_08BITS 1 #define MAXIM2C_I2C_REG_VALUE_16BITS 2 #define MAXIM2C_I2C_REG_VALUE_24BITS 3 /* I2C Device ID */ enum { MAXIM2C_I2C_DES_DEF, /* Deserializer I2C address: Default */ MAXIM2C_I2C_SER_DEF, /* Serializer I2C address: Default */ MAXIM2C_I2C_SER_MAP, /* Serializer I2C address: Mapping */ MAXIM2C_I2C_CAM_DEF, /* Camera I2C address: Default */ MAXIM2C_I2C_CAM_MAP, /* Camera I2C address: Mapping */ MAXIM2C_I2C_DEV_MAX, }; /* i2c register array end */ #define MAXIM2C_REG_NULL 0xFFFF struct maxim2c_i2c_regval { u16 reg_len; u16 reg_addr; u32 val_len; u32 reg_val; u32 val_mask; u8 delay; }; /* seq_item_size = reg_len + val_len * 2 + 1 */ struct maxim2c_i2c_init_seq { struct maxim2c_i2c_regval *reg_init_seq; u32 reg_seq_size; u32 seq_item_size; u32 reg_len; u32 val_len; }; #endif /* __MAXIM2C_I2C_H__ */ //#include "maxim2c_link.h" #ifndef __MAXIM2C_LINK_H__ #define __MAXIM2C_LINK_H__ //#include "maxim2c_i2c.h" /* Link cable */ enum maxim2c_link_cable { MAXIM2C_CABLE_COAX = 0, MAXIM2C_CABLE_STP, }; /* Link Type */ enum maxim2c_link_type { MAXIM2C_GMSL1 = 0, MAXIM2C_GMSL2, }; /* Link Mode */ enum maxim2c_link_mode { MAXIM2C_GMSL_PIXEL = 0, MAXIM2C_GMSL_TUNNEL, }; /* I2C Remote Control Port */ enum { MAXIM2C_I2C_PORT0 = 0, MAXIM2C_I2C_PORT1, MAXIM2C_I2C_PORT2, MAXIM2C_I2C_PORT_MAX, }; /* Link SIO ID: 0 ~ 3 */ enum { MAXIM2C_LINK_ID_A = 0, MAXIM2C_LINK_ID_B, MAXIM2C_LINK_ID_MAX, }; /* Link Bit Mask: bit0 ~ bit3 */ #define MAXIM2C_LINK_MASK_A BIT(MAXIM2C_LINK_ID_A) #define MAXIM2C_LINK_MASK_B BIT(MAXIM2C_LINK_ID_B) #define MAXIM2C_LINK_MASK_ALL GENMASK(MAXIM2C_LINK_ID_B, MAXIM2C_LINK_ID_A) /* Link Receiver Rate */ enum maxim2c_link_rx_rate { MAXIM2C_LINK_RX_RATE_3GBPS = 0, MAXIM2C_LINK_RX_RATE_6GBPS, }; /* Link Transmitter Rate */ enum maxim2c_link_tx_rate { MAXIM2C_LINK_TX_RATE_187_5MPS = 0, }; struct maxim2c_link_cfg { u8 link_enable; u8 link_type; u8 link_rx_rate; u8 link_tx_rate; struct maxim2c_i2c_init_seq link_init_seq; }; typedef struct maxim2c_gmsl_link { u8 link_enable_mask; u8 link_type_mask; u8 link_locked_mask; u8 link_vdd_ldo1_en; struct maxim2c_link_cfg link_cfg[MAXIM2C_LINK_ID_MAX]; } maxim2c_gmsl_link_t; #endif /* __MAXIM2C_LINK_H__ */ //#include "maxim2c_video_pipe.h" #ifndef __MAXIM2C_VIDEO_PIPE_H__ #define __MAXIM2C_VIDEO_PIPE_H__ //#include "maxim2c_i2c.h" /* Video Pipe In ID: 0 ~ 3 */ enum { MAXIM2C_PIPE_I_ID_X = 0, MAXIM2C_PIPE_I_ID_Y, MAXIM2C_PIPE_I_ID_Z, MAXIM2C_PIPE_I_ID_U, MAXIM2C_PIPE_I_ID_MAX, }; /* Video Pipe Out ID: 0 ~ 1 */ enum { MAXIM2C_PIPE_O_ID_Y = 0, MAXIM2C_PIPE_O_ID_Z, MAXIM2C_PIPE_O_ID_MAX, }; /* Video Pipe Out Config */ struct maxim2c_pipe_cfg { u8 pipe_enable; u8 pipe_idx; u8 link_idx; struct maxim2c_i2c_init_seq pipe_init_seq; }; typedef struct maxim2c_video_pipe { u8 pipe_enable_mask; struct maxim2c_pipe_cfg pipe_cfg[MAXIM2C_PIPE_O_ID_MAX]; struct maxim2c_i2c_init_seq parallel_init_seq; } maxim2c_video_pipe_t; #endif /* __MAXIM2C_VIDEO_PIPE_H__ */ //#include "maxim2c_mipi_txphy.h" #ifndef __MAXIM2C_MIPI_TXPHY_H__ #define __MAXIM2C_MIPI_TXPHY_H__ /* MIPI TXPHY ID: 0 ~ 3 */ enum { MAXIM2C_TXPHY_ID_A = 0, MAXIM2C_TXPHY_ID_B, MAXIM2C_TXPHY_ID_C, MAXIM2C_TXPHY_ID_D, MAXIM2C_TXPHY_ID_MAX, }; /* MIPI TXPHY Bit Mask: bit0 ~ bit3 */ #define MAXIM2C_TXPHY_MASK_A BIT(MAXIM2C_TXPHY_ID_A) #define MAXIM2C_TXPHY_MASK_B BIT(MAXIM2C_TXPHY_ID_B) #define MAXIM2C_TXPHY_MASK_C BIT(MAXIM2C_TXPHY_ID_C) #define MAXIM2C_TXPHY_MASK_D BIT(MAXIM2C_TXPHY_ID_D) #define MAXIM2C_TXPHY_MASK_ALL GENMASK(MAXIM2C_TXPHY_ID_D, MAXIM2C_TXPHY_ID_A) /* MIPI TXPHY Type */ enum { MAXIM2C_TXPHY_TYPE_DPHY = 0, MAXIM2C_TXPHY_TYPE_CPHY, }; /* MIPI TXPHY Mode */ enum { MAXIM2C_TXPHY_MODE_2X4LANES = 0, /* PortA: 1x4Lanes, PortB: 1x4Lanes */ MAXIM2C_TXPHY_MODE_2X2LANES, /* PortA: 2Lanes, PortB: 2Lanes */ }; /* MIPI TXPHY DPLL */ enum { MAXIM2C_TXPHY_DPLL_PREDEF = 0, MAXIM2C_TXPHY_DPLL_FINE_TUNING, }; struct maxim2c_txphy_cfg { u8 phy_enable; u8 phy_type; u8 auto_deskew; u8 data_lane_num; u8 data_lane_map; u8 vc_ext_en; u8 tunnel_enable; u8 tunnel_vs_wait; u8 tunnel_dest; u8 clock_master; u8 clock_mode; }; typedef struct maxim2c_mipi_txphy { u8 phy_mode; /* mipi txphy mode */ u8 force_clock_out_en; /* Force all MIPI clocks running */ struct maxim2c_txphy_cfg phy_cfg[MAXIM2C_TXPHY_ID_MAX]; } maxim2c_mipi_txphy_t; #endif /* __MAXIM2C_MIPI_TXPHY_H__ */ //#include "maxim2c_remote.h" #ifndef __MAXIM2C_REMOTE_H__ #define __MAXIM2C_REMOTE_H__ //#include "maxim2c_i2c.h" struct maxim2c_remote; struct m