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先甩个最核心的计数器代码镇楼

news 2026/8/29 11:14:43

用FPGA实现数字时钟，使用verilog代码实现。平台：vivado 仿真：multisim 功能：实现24小时制，时钟显示，可设置初始值。有代码，仿真代码，约束文件全套

module time_counter( input clk_1Hz, input rst, input [5:0] set_hour, input [5:0] set_min, input load, output reg [5:0] hour, output reg [5:0] min, output reg [5:0] sec ); always @(posedge clk_1Hz or posedge rst) begin if(rst) begin hour <= 6'd0; min <= 6'd0; sec <= 6'd0; end else if(load) begin // 初始值装载 hour <= set_hour; min <= set_min; sec <= 6'd0; end else begin if(sec == 6'd59) begin sec <= 0; if(min == 6'd59) begin min <= 0; hour <= (hour == 6'd23) ? 0 : hour + 1; end else begin min <= min + 1; end end else begin sec <= sec + 1; end end end endmodule

这段代码有个骚操作：用三进制条件运算符处理小时进位。注意第21行那个(hour == 6'd23) ? 0 : hour + 1，比if-else写法省了至少三行代码，适合装逼时使用。

分频模块才是真正的节奏大师：

module clk_div( input clk, input rst, output reg clk_1Hz, output reg clk_1kHz ); reg [26:0] cnt_1Hz; reg [15:0] cnt_1kHz; // 1Hz生成（实际使用要改分频系数） always @(posedge clk or posedge rst) begin if(rst) begin cnt_1Hz <= 0; clk_1Hz <= 0; end else if(cnt_1Hz == 27'd49_999_999) begin // 仿真时改小数值 cnt_1Hz <= 0; clk_1Hz <= ~clk_1Hz; end else begin cnt_1Hz <= cnt_1Hz + 1; end end // 1kHz生成用于数码管扫描 always @(posedge clk or posedge rst) begin if(rst) begin cnt_1kHz <= 0; clk_1kHz <= 0; end else if(cnt_1kHz == 16'd49_999) begin cnt_1kHz <= 0; clk_1kHz <= ~clk_1kHz; end else begin cnt_1kHz <= cnt_1kHz + 1; end end endmodule

重点看第14行的注释——仿真时记得把分频系数改小！不然等仿真结果等到天荒地老。亲身踩坑经验：曾经用实际参数仿真，结果等了三小时才跑完一秒...

用FPGA实现数字时钟，使用verilog代码实现。平台：vivado 仿真：multisim 功能：实现24小时制，时钟显示，可设置初始值。有代码，仿真代码，约束文件全套

数码管驱动要玩转视觉暂留：

module seg_driver( input clk_1kHz, input [5:0] hour, input [5:0] min, input [5:0] sec, output reg [7:0] seg, output reg [5:0] sel ); reg [2:0] scan_cnt; reg [3:0] data; // 数码管扫描计数器 always @(posedge clk_1kHz) begin scan_cnt <= (scan_cnt == 3'd5) ? 0 : scan_cnt + 1; end // 根据扫描位置选择显示内容 always @(*) begin case(scan_cnt) 0: begin data = sec%10; sel = 6'b111110; end 1: begin data = sec/10; sel = 6'b111101; end 2: begin data = min%10; sel = 6'b111011; end 3: begin data = min/10; sel = 6'b110111; end 4: begin data = hour%10; sel = 6'b101111; end 5: begin data = hour/10; sel = 6'b011111; end default: begin data = 4'd0; sel = 6'b111111; end endcase end // 七段译码 always @(*) begin case(data) 0: seg = 8'b11000000; // 带小数点 1: seg = 8'b11111001; 2: seg = 8'b10100100; 3: seg = 8'b10110000; 4: seg = 8'b10011001; 5: seg = 8'b10010010; 6: seg = 8'b10000010; 7: seg = 8'b11111000; 8: seg = 8'b10000000; 9: seg = 8'b10010000; default: seg = 8'b11111111; endcase end endmodule

数码管扫描用了六个位选信号，每个时钟周期切换一个数字。注意第24行的带小数点设计，这样秒的个位数显示时会有点号闪烁效果，实测逼格提升50%。

约束文件示例（具体引脚根据开发板调整）：

set_property PACKAGE_PIN R4 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] set_property PACKAGE_PIN U7 [get_ports {seg[7]}] ... set_property PACKAGE_PIN V9 [get_ports {sel[5]}]

仿真测试用例要搞事情：

`timescale 1ns / 1ps module tb_time_counter; reg clk; reg rst; reg load; reg [5:0] set_hour; reg [5:0] set_min; wire [5:0] hour; wire [5:0] min; wire [5:0] sec; time_counter uut(.*); initial begin clk = 0; forever #5 clk = ~clk; end initial begin rst = 1; #100; rst = 0; // 测试初始值装载 set_hour = 6'd23; set_min = 6'd59; load = 1; #100; load = 0; // 等待进位触发 #200000000; $finish; end endmodule

这个仿真用例故意在23:59时装载初始值，观察是否正常跳转到00:00。注意第21行的等待时间要根据实际分频系数调整。

最后说两个血泪经验：