Formality：黑盒(black box)
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Formalityhttps://blog.csdn.net/weixin_45791458/category_12841971.html?spm=1001.2014.3001.5482
简介
在使用Formality时，黑盒(black box)的概念很重要，指的是一个其功能未知的设计。黑盒通常用于设计中不可综合的组件，包括RAM、ROM、模拟电路和硬核IP等。它也是需要匹配的对象之一，必须确保参考设计和实现设计之间存在一一对应的映射，黑盒输入引脚被视为比较点，而黑盒输出引脚被视为普通匹配点，关于这两者的概念，详见下面这篇博客。
Formality：匹配(match)是如何进行的？https://chenzhang.blog.csdn.net/article/details/144404964
哪些情况会产生黑盒？
只有端口定义而没有其他定义的设计（或者说STUB模块）
例1所示的设计black_box只有端口定义，因此被认为是黑盒设计，这种黑盒拥有完整的引脚定义（名字和方向）。
// 例1 module black_box ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); endmodule module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( .clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out) ); endmodule下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/top_module Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 22:59:54 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### DESIGN LIBRARY - r:/WORK ################################################################## Type Design Name ---- ---------- e black_box Instances : 1 of 1 ------------------------ r:/WORK/top_module/u_black_box功能信息不包含库文件(.db)中的设计
以存储器为例，Memory Compiler会生成含引脚和时序信息的.lib文件，而经过Library Compiler编译后的.db文件中一般只含有一个存储器宏单元，且不包含功能信息，如下报告所示，其中的b属性代表该宏单元没有功能信息。
lc_shell> report_lib ram4x32_max ram4x32 **************************************** Report : library Library: ram4x32_max Version: O-2018.06-SP1 Date : Mon Jan 27 23:04:54 2025 **************************************** Library Type : Technology Tool Created : W-2004.12 Date Created : .18-Dec-2001 Library Version : .1.0 Comments : Unit Area representation == 6.0516 sq.micron Components: Attributes: af - active falling ah - active high al - active low ar - active rising b - black box (function unknown) Cell Footprint Attributes ------------------------------------------- ram4x32 "ram4x32" b, d, mo, s, u例2所示的设计ram4x32是来自逻辑库的宏单元，因此被认为是黑盒设计，这种黑盒拥有完整的引脚定义（名字和方向）。
// 例2 module ram4x32_top( input wire CE1, input wire CE2, input wire OEB1, input wire OEB2, input wire CSB1, input wire CSB2, input wire WEB1, input wire WEB2, input wire [4:0] A1, input wire [4:0] A2, input wire [3:0] I1, input wire [3:0] I2, output wire [3:0] O1, output wire [3:0] O2 ); ram4x32 U_ram4x32 ( .CE1(CE1), .CE2(CE2), .OEB1(OEB1), .OEB2(OEB2), .CSB1(CSB1), .CSB2(CSB2), .WEB1(WEB1), .WEB2(WEB2), .A1(A1), .A2(A2), .I1(I1), .I2(I2), .O1(O1), .O2(O2) ); endmodule下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/ram4x32_top Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 22:55:14 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### TECH LIBRARY - r:/RAM4X32_MAX ################################################################## Type Design Name ---- ---------- m ram4x32 Instances : 1 of 1 ------------------------ r:/WORK/ram4x32_top/U_ram4x32变量hdlin_unresolved_modules定义为black_box时未解析的设计
当设计的所有定义都缺失时，默认情况下（即变量hdlin_unresolved_modules定义为error时）在使用set_top命令进行展开时，会报错“Error: Unresolved references detected during link.”。如果将变量hdlin_unresolved_modules定义为black_box，则会将所有未解析的设计当做黑盒设，并提示“Warning: 1 blackbox designs were created for missing references.”。
如果使用命名端口连接，则该黑盒设计拥有引脚名字的定义而没有引脚方向的定义，如例3所示。
// 例3 module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( .clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out) ); endmodule如果使用位置端口连接，则该设计没有引脚名字和引脚方向的定义，如例4所示。
// 例4 module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( clk, reset, data_in, data_out, ); endmodule对于引脚名字未定义的情况，Formality会使用默认的引脚名(p1、p2、p3...)；对于引脚方向未定义的情况，Formality会尝试根据连接关系和局部几何结构智能地、保守地猜测引脚方向，并提示“Warning: 19 black-box pins of unknown direction found; see formality.log for list”。如果工具无法确定引脚方向，它会假设该引脚是双向的，这可能会导致多驱动线网。此外，可以使用set_direction命令来显式定义引脚方向。
下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/top_module Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 23:02:29 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### TECH LIBRARY - r:/FM_BBOX ################################################################## Type Design Name ---- ---------- u black_box Instances : 1 of 1 ------------------------ r:/WORK/top_module/u_black_box使用变量hdlin_interface_only定义的设计
在读取设计文件时，变量hdlin_interface_only指定的设计将被当做黑盒设计，这种黑盒拥有完整的引脚定义（名字和方向），如例5所示（如果变量hdlin_interface_only设置时，该设计已经读取，但还未使用set_top命令进行展开，其也会被当做黑盒设计，但此时report_black_boxes命令的结果将不被标记为i而是e）。
// 例5 // 在使用set_top命令前设置变量hdlin_interface_only为black_box module black_box ( input wire clk, input wire reset, input wire [7:0] data_in, output reg [7:0] data_out ); always @(posedge clk or posedge reset) begin if (reset) data_out <= 8'b0; else data_out <= data_in; end endmodule module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( .clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out) ); endmodule下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/top_module Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 23:13:27 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### DESIGN LIBRARY - r:/WORK ################################################################## Type Design Name ---- ---------- i black_box Instances : 1 of 1 ------------------------ r:/WORK/top_module/u_black_box使用set_black_box命令指定的设计
使用set_black_box命令可以将一个设计设置为黑盒设计，无论此时是否已使用set_top命令进行展开，这种黑盒拥有完整的引脚定义（名字和方向），如例6所示。
// 例6 // 使用set_black_box命令设置black_box设计为黑盒 module black_box ( input wire clk, input wire reset, input wire [7:0] data_in, output reg [7:0] data_out ); always @(posedge clk or posedge reset) begin if (reset) data_out <= 8'b0; else data_out <= data_in; end endmodule module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( .clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out) ); endmodule下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/top_module Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 23:20:41 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### DESIGN LIBRARY - r:/WORK ################################################################## Type Design Name ---- ---------- s black_box Instances : 1 of 1 ------------------------ r:/WORK/top_module/u_black_box使用create_cutpoint_blackbox命令创建的设计
// 例7 // 使用create_cutpoint_blackbox命令创建cut-point黑盒 // create_cutpoint_blackbox cut_blackbox [get_pins r:/WORK/top_module/u_black_box/data_in[6]] module black_box ( input wire clk, input wire reset, input wire [7:0] data_in, output reg [7:0] data_out ); always @(posedge clk or posedge reset) begin if (reset) data_out <= 8'b0; else data_out <= data_in; end endmodule module top_module ( input wire clk, input wire reset, input wire [7:0] data_in, output wire [7:0] data_out ); black_box u_black_box ( .clk(clk), .reset(reset), .data_in(data_in), .data_out(data_out) ); endmodule下面是使用report_black_boxes命令进行报告的结果。
Formality (setup)> report_black_boxes ************************************************** Report : black_boxes Reference : r:/WORK/top_module Implementation : <None> Version : W-2024.09-SP2 Date : Thu Jan 30 23:20:41 2025 ************************************************** Information: Implementation design is not set. (FM-149) Information: Reporting black boxes for current reference design. (FM-184) ___________________________________________________ | | | Legend: | | Black Box Attributes | | s = Set with set_black_box command | | i = Module read with -interface_only | | u = Unresolved design module | | e = Empty design module | | * = Unlinked design module | | ut = Unread tech cells pins | | L = Linked to non-black box design | | cp = Cutpoint blackbox | | ir = Internal rounded blackbox | | f = Formality Power Model | | m = Technology Macro cell (.db) | |___________________________________________________| ################################################################## #### DESIGN LIBRARY - r:/WORK ################################################################## Type Design Name ---- ---------- cp black_box Instances : 1 of 1 ------------------------ r:/WORK/top_module/cut_blackbox